1. Field of the Invention
The present invention is related to a data receiver and data communication system.
2. Description of the Related Art
In order to satisfy demands of a large capacity and high speed data transmission, numerous high speed interface standards exist in practical use. The high speed interface standards mostly apply to a serial transmission method. In a serial transmission, data are transmitted based on a frequency defined beforehand. A clock signal of a frequency is superimposed with the data to be transmitted. A data receiver extracts the clock signal, and recovers the data based on the clock signal. A circuit for conducting a restore operation is called a “clock data recovery” (hereinafter, abbreviated as a “CDR”).
In a conventional CDR circuit, a PLL (Phase-Locked Loop) circuit is generally used. The PLL circuit is controlled so that an oscillator clock of a VCO (Voltage-Controlled Oscillator) in the PLL circuit synchronizes with a phase of received data. The oscillator clock is extracted as a recovery clock. By latching the received data in which the recovery clock is determined as a reference, the received data are accurately recovered.
An oversampling type CDR circuit is proposed (refer to Patent Document 1), for example). The oversampling type CDR circuit generates multiphase clocks in which phases are shifted at equal intervals based on a reference clock. The oversampling data are acquired by sampling input data. The oversampling type CDR circuit detects timing at which a logic is reversed from a bit sequence of the oversampling data, and restores the clock and the data based on the result. By adopting this configuration, since a circuit other than the multiphase clock generator can be configured by using a digital circuit, the circuit can be realized relatively easily.
As a jitter caused by the transmission channel, Inter-Symbol Interference (ISI) is known. Conventionally, an equalizer is used to reduce ISI. In the equalizer, by realizing a filter having a reverse characteristic of the frequency characteristic which causes ISI, the frequency characteristic of the data transmission in a data band is formed to be flat. For instance, the reverse characteristic may be a high pass characteristic in a case in which the frequency characteristic of the transmission channel is the low pass characteristic. By this configuration, the jitter caused by ISI is reduced.
Recently, in order to respond to diversity of a data transmission rate and diversity of the data transmission channel, an adaptive equalizing technology has been developed to adaptively adjust an equalizing amount. Especially, a Decision Feedback Equalizer (DFE) is largely used as the adaptive equalizer in a receiving circuit of a serial transmission system (see Patent Documents 2 and 3).
Moreover, a signal processing apparatus, in which the oversampling type CDR circuit and the adaptive equalizing technology are combined, is known. That is, Patent Document 4 discloses an equalizing processing apparatus of the oversampling type CDR circuit in which its object is to reduce the jitter caused by ISI. Accordingly to the equalizing processing apparatus, received data are binalized, a digital signal process is conducted to binalize the data, and the binalized data are further binalized based on a result of the digital signal process, so as to realize an adaptive equalizing.